An atomic operation is an operation that appears as a single change to the “external” state (i.e., external to the parts of the processor that are performing the transaction) of a processor. For example, an atomic operation can include (1) reading a value from memory, (2) changing that value, and (3) writing the changed value back to memory. If these three steps are part of an atomic operation, they all must be performed; otherwise, none of these steps are performed. Atomic operations may ensure that a memory location that was read is locked from being modified by another thread. These types of features are important for memory locations that are writable and shared among multiple threads.
Prior art systems locked a memory location using a Load Link (LL) instruction (also known as a Load Lock or Locked Load) to a particular memory address. The LL instruction (1) causes loading of the data at the memory address into a register and (2) sets a link status bit (LLBIT). Later, a Store Conditional (SC) instruction is executed, which first checks the LLBIT status, and if LLBIT remains set, then the SC instruction continues and will commit the updated value into memory. If the LLBIT was cleared, then the SC instruction will fail, and the atomic operation, starting at the LL instruction, will repeat. In a multiprocessor system, if a cache line holding data that the LL instruction is loaded from is subsequently written or has another processor invalidating that line, then the SC instruction will fail. In a multi-processor system, if some other processor or agent modifies the location protected by the LL bit, the LL bit will be cleared. What is needed is a better way to access memory.